(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming a diffusion barrier layer comprising a TaSiN layer and a method of forming a metal interconnection line using the same.
(b) Description of the Related Art
Recently, during a process of manufacturing a semiconductor device, a diffusion barrier has frequently been formed in order to prevent a metal material from diffusing into silicon and/or an insulating layer (and often, vice versa). Such a diffusion barrier layer is desired to have a more uniform and lower resistivity due to higher integration of a semiconductor device. More particularly, when a scale of a semiconductor device is 60 nm or less, a diffusion barrier layer is required to have a thickness of about 50 Å or less in order to decrease a delay time caused by contact resistance.
Recently, a ternary nitride layer such as a tantalum-silicon-nitride (TaSiN) layer has more frequently been used as a diffusion barrier layer than a binary nitride layer, such as a titanium nitride (TiN) or tantalum nitride (TaN) layer, because a ternary nitride layer containing Si shows better performance than a binary nitride layer. When a TaN layer is deposited by a physical vapor deposition (PVD) method, the TaN layer generally has a thickness of at least about 50 Å to enable its use as a diffusion barrier for a device having a scale of 60 nm or less. Therefore, a TaN layer formed by the PVD method may show poor step coverage. Similarly, when a TaSiN layer is deposited by a PVD method, there is a merit that an excellent TaSiN layer having little or no impurities can be formed by a simple process. However, when a TaSiN layer is used as a diffusion barrier for a device having a scale of 60 nm or less, it may also show poor step coverage.
Therefore, much research is under investigation for depositing a TaSiN layer by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method rather than a PVD method. However, such alternative methods may have drawbacks including a complicated and/or relatively slow process and a low yield.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art or other information that is already known in this or any other country to a person of ordinary skill in the art.